The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 08, 1990
Filed:
Jan. 19, 1988
Applicant:
Inventors:
Tho T Vu, New Brighton, MN (US);
Danh N Tran, Irvine, TX (US);
Assignee:
Honeywell Inc., Minneapolis, MN (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307448 ; 307450 ; 307356 ; 307554 ; 307310 ;
Abstract
A feedback source coupled FET logic (FSCL) circuit having an internal reference voltage provided by the output of one FET of a pair of FET's, connected via a source follower FET to the input of the other FET of the pair. FSCL logic circuitry has advantages over known source coupled FET logic (SCFL) circuitry in that FSCL has higher density of functions for a given area of integrated circuitry, lower voltage drift with temperature change, higher voltage gain, higher noise margin, and larger fanout loading. The output of one FET, via a source follower FET, is connected to the input of the other FET of the pair.