Filter circuit for generating a vco control voltage responsive to the

Abstract

A filter circuit is driven by two digital phase responsive output signals from the frequency/phase discriminator of a phase-locked loop (PLL) circuit. The controlled current paths of a first n-conducting transistor, a second n-conducting transistor, a second p-conducting transistor and a first p-conducting transistor are connected in that order between the plus and minus poles of a source of supply voltage. The common connection between the controlled current paths of the second n-conducting transistor and the second p-conducting transistor is connected to the output of the filter circuit. The second n-conducting transistor and the second p-conducting transistor are connected as diodes with the gate of the second n-conducting transistor connected to the common connection between the first n-conducting transistor and the second n-conducting transistor, and with the gate of the second p-conducting transistor connected to the common connection between the first p-conducting transistor and the second p-conducting transistor. The output of the filter circuit is connected across a series RC circuit to the minus pole of the source of supply voltage. The first digital signal from the frequency/phase discriminator is fed to the gate of the second n-conducting transistor via a capacitor. The second digital signal from the frequency/phase discriminator is fed to the gate of the second p-conducting transistor via the series arrangement of an inverter and a capacitor. The gate of the first n-conducting transistor and the gate of the first p-conducting transistor are applied to the common connection of the resistor and the capacitor of the RC circuit. In that way the range of control of the output voltage from the filter circuit is substantially greater than that of the supply voltage, and the coupling-in of the two digital signals to the output voltage is substantially avoided.