The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 1990
Filed:
Oct. 19, 1988
Takeo Obata, Osaka, JP;
Ricoh Company, Ltd., Tokyo, JP;
Abstract
A programmable logic array (PLA) whose AC characteristics such as an input-to-output delay characteristic can be measured includes a plurality of input lines, a plurality of product term lines, a plurality of non-volatile memory elements, and a test input line to which a test signal may be applied. Those non-volatile memory elements which are connected to the input lines other than the test input line are turned OFF in a test mode, while turning all product term lines other than the product term line whose AC characteristics are to be measured, to a low level. Only those memory elements whose AC characteristics are to be measured are operable in an ON-OFF fashion and only the product term line to be measured is ready to have a low level or a high level. When a test signal is applied to the test input line, it is routed to the operable memory elements and product term line only.