Method of manufacturing an insulated gate field effect transistor dmos

Abstract

A method of manufacturing an insulated gate field effect transistor is described. The method comprises providing a gate layer (6) on an insulating layer (12) on one surface (4) of a semiconductor body (1) and source regions (2) of one conductivity type within a respective body region (14), a portion of each body region (14) underlying a portion of the gate layer to provide a channel area extending between the source region (2) and a drain region (3) meeting another surface (5) of the semiconductor body opposite the one surface (4). Each source region (2) is shorted to the corresponding body region (14) by opening a contact window (15) in the insulating layer on the one surface so as to expose a surface of the source region (2), providing resist masking regions (16) extending completely across the contact window in one direction so as to define an exposed area of the source region which is not covered by either the masking regions or the insulating layer ( 12), and has a periphery defined partly by the contact window and partly by the masking region(s), etching away the exposed area of the source region (2) to expose an underlying area of the body region (14), removing the masking regions and providing metallization within the contact window (15) to short the exposed area of the body region to the source region.