Latch-up control for a cmos memory with a pumped well

Abstract

A CMOS DRAM has an array in a well which is pumped to a voltage greater than the power supply voltage. The transfer devices of the memory cells in the array are of a conductivity type opposite to that of the well. The transfer devices each have a source/drain of the opposite conductivity type to that of the well which is connected to a bit line. The bit line will tend to rise in voltage at power-up which has the potential of forward biasing the PN junction between the source/drain and the well. The bit line rise is due to a word-line rise the rate of which is controlled so that the bit line rise does not exceed the rise in array voltage. The bit lines are ensured of being separated in voltage at the beginning of the first active cycle by enabling the N channel portion of the sense amplifier during power-up. The P channel portion of the sense amplifier is disabled during power-up to avoid too rapid of a rise in voltage on the bit lines. Equalization of the bit lines is suppressed during the first cycle to avoid having the sense amplifier face the high current drain condition of little or no voltage differential at low voltage.