Integrated d/a converter including means for reducing glitches

Abstract

An integrated digital-to-analogue (D/A) converter circuit provided with a device for reducing glitches. The D/A converter converts control signals having n binary states Bn into analogue signals and comprises n differential pairs Pn of transistors T1n and T2n connected to n current generators which supply currents of a value In weighted according to the binary weights 2.sup.n of the binary states Bn. The transistors T1n receives their respective binary control signals and the transistors T2n receive the respective binary control signals inverse to the preceding signals. The triggering instant of the differential pairs at a leading edge of the control signal is shifted over the triggering instant at a leading edge of the control signal in that a shift of the triggering thresholds of the transistors T1n with respect to the transistors T2n is effected over a constant value Vd obtained by the device for reducing glitches and constituted by resistors Rn connected in series with the emitters of the transistors of one of the series of transistors T1n or T2n in such a manner that Rn..sup.In/.sub.2 =Vd.