The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 1990

Filed:

Sep. 23, 1988
Applicant:
Inventors:

Douglas C Galbraith, Fremont, CA (US);

Michael G Ahrens, Sunnyvale, CA (US);

Assignee:

Actel Corporaton, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F / ; H03K / ;
U.S. Cl.
CPC ...
307530 ; 307451 ; 307279 ; 365205 ; 365207 ;
Abstract

A high speed static single ended sense amplifier is disclosed, including, an input node, an output node, a first P-channel input transistor having its source connected to a source of positive voltage, its drain connected to the input node and its gate connected to a feedback node, a first N-channel input transistor having its drain connected to the input node, its source connected to a source of negative voltage and its gate connected to the feedback node, a first output P-channel transistor having its source connected to a source of positive voltage, its drain connected to the output node, and its gate connected to the feedback node, a first N-channel output transistor having its drain connected to the output node, its source connected to a source of positive voltage and its gate connected to the feedback node, an N-channel feedback transistor having its gate connected to the output node, its drain connected to a source of positive voltage and its source connected to the feedback node, a capacitive voltage divider connected between the source of negative voltage, the source of positive voltage, and the input node, the capacitive voltage divider including a parasitic capacitance and a P-channel gate capacitor connected between the input node and one of the positive or negative voltage sources, the capacitance ratio of the capacitive voltage divider being such as to give the same voltage divider ratio as the voltage divider ratio resulting from the first P-channel MOS input transistor and the first N-channel MOS input transistor.


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