The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 1990

Filed:

Dec. 30, 1988
Applicant:
Inventors:

Bruce M Steinetz, Broadview Heights, OH (US);

Paul J Sirocky, Middleburg Heights, OH (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B64D / ; F16J / ;
U.S. Cl.
CPC ...
23926511 ; 277 34 ; 277158 ;
Abstract

This device is concerned with sealing the sliding interfaces between structural panels that are roughly perpendicular to each other or whose edges are butted against one another. The gap which the seal element must seal is not uniform along the seal length requiring significant seal flexibility. The seal 10 is mounted in a rectangular groove 14 in a moveable structural panel 16. The seal comprises a plurality of rectangular shaped wafers 12 stacked next to one another and preloaded in the axial direction to minimize leakage between wafers. The wafers are laterally preloaded to maintain sealing contact along the wafer faces which engage the adjacent wall of a sidewall 18 using one of several approaches, such as the pressurized linear bellows 22. The seal accomodates distortions in the adjacent panel by relative sliding between adjacent wafers. Leakage between wafers is further minimized with good wafer surface finishes. Leakage between the seal nose and the adjacent structural panel is minimized when sealing against a distorted sidewall with relatively thin wafers and suitable seal preload apparatus. Leakage behind the seal is minimized with good groove tolerances and good sealing contact between the preload system and the back of the peripheral edge of the wafers.


Find Patent Forward Citations

Loading…