Single instruction multiple data (simd) cellular array processing

Abstract

A cellular array having a plurality of processor cells disposed on a chip and interconnected by an internal bus includes data bus couplers for bidirectionally coupling to one or more external buses. The data bus couplers selectively couple buses having multiple logic levels. The number of logic levels on the coupled buses may differ. The internal bus may comprise a plurality of parallel data lines each having two-level logic such as binary data, whereas the external buses may have four-level logic represented by four voltage levels. Each data bus coupler has two-bit A/D and D/A converters parallelly connected to selectively convert two bits of two-level logic data to multiple level data and vice versa. The data bus coupler also has a logic level selector circuit using bidirectional gates for selective operation between buses having similar or dissimilar logic levels. The data bus couplers may be associated with pins organized in a regular architecture and used in connection with bedirectional transceivers to multiplex data corresponding to a multiplicity of external buses onto the internal bus and vice versa. Using this pin architecture the data bus couplers may be dynamically configured to support a collection of two-level and four-level external buses to suit the interfacing needs of the chip.