The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 1990

Filed:

Mar. 23, 1988
Applicant:
Inventors:

Suzanne E Genz, Sherborn, MA (US);

John R Fierke, Southboro, MA (US);

Assignee:

Data Translation, Inc., Marlboro, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ; G06F / ;
U.S. Cl.
CPC ...
358 75 ; 358 78 ; 364764 ;
Abstract

Circuitry for converting digital red, green, blue (RGB) inputs into digital saturation and hue outputs comprising hardwired digital components connected to receive the digital RGB inputs and to perform arithmetic manipulations of them so as to provide a digital saturation output representing saturation for the RGB inputs and to provide a digital first intermediate output, and a first look-up memory storing digital hue data representing hue of the digital RGB inputs at addresses corresponding to values of the digital first intermediate output, the look-up memory being connected to the hardwired digital components to be addressed by the digital intermediate output, the memory providing a digital hue output. Also disclosed are: circuitry for converting digital hue data, digital saturation data, and brightness-related digital data into digital RGB outputs using a further look-up memory that is addressed by the hue data and provides an intermediate output used with the saturation data and brightness-related data by hardwired components to provide digital RGB outputs; a fixed point divider including bit subcircuits that each include an adder, a multiplexer and a bit shifting element; and a floating point divider that decodes dividend and divisor signals to provide a quotient exponent signal and left-justifies the dividend and divisor signals to obtain dividend mantissa and divisor mantissa signals that are divided to obtain a mantissa quotient signal.


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