Digital phase-locked loop system

Abstract

A digital phase-locked loop system having an oscillator which generates a clock signal of a stationary frequency, a frequency divider which frequency-divides the clock signal to produce a phase-locked loop clock signal, a phase difference detector which detects a phase difference between an input signal and the phase-locked loop clock signal and outputs a phase difference detection signal, and a frequency dividing rate setting device to set a frequency dividing rate corresponding to the phase difference in response to the phase difference detection signal and apply the rate to the frequency divider. The phase difference detector includes a first counter to detect a phase difference at a leading edge of the clock signal from the oscillator and a second counter to detect it at a trailing edge of the clock signal. The frequency dividing rate setting device includes an adder to add the phase differences detected by the first and second counters, a latch to hold an addition result produced by the adder, and a decoder to decode the frequency dividing rate corresponding to the addition result held by the latch. The frequency divider frequency-divides the clock signal according to the frequency dividing rate decoded by the decoder and newly generates a phase-locked loop clock signal.