Method and apparatus for decoding error correcting code

Abstract

A received signal train V(X) having a code length of 19 bits, in which an error correcting code is added on the basis of a generator polynominal G(X) of degree 11, is converted into a signal train V.sub.I (X) obtained by reversing an arrangement order from MSB to LSB in V(X) so that LSB in V(X) is positinoed in MSB in V.sub.I (X), . . . , and MSB in V(X) is positioned in LSB in V.sub.I (X) and then, the signal train V.sub.I (X) is divided by an inverse generator polynominal G.sub.I (X) of the generator polynominal G(X). A judgement is made on the number of '1's in the resulting 11-bit syndrome S.sub.I (X). If the number is one or zero, single-bit error correction is performed by MOD2 addition of the received signal train V(X) and the syndrome S.sub.I (X). On the other hand, remaining 6 bits in occurrence of a primary error are read out from a ROM 13 with the address of particular 5 bits in the syndrome S.sub.I (X). A judgement is made on coincidence of the 6 bits read out and corresponding 6 bits in the actually calculated syndrome S.sub.I (X). As a result, a judgement is made that the received signal train V(X) includes a secondary error or an error of higher degree if non-coincidence is indicated and if it is determined that the number of '1's in the syndrome S.sub.I (X) is two or more.