The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 1990
Filed:
Dec. 14, 1988
Chekib Akrout, Orangis, FR;
Pierre Coppens, Savigny le Temple, FR;
Bernard Denis, Mennecy, FR;
Pierre-Yves Urena, Vence, FR;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND). The improved reference voltage of the present invention significantly reduces both consumed silicon area and restore time.