The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 1990
Filed:
Mar. 11, 1987
Rudolf Bitzinger, Munich, DE;
Walter Engl, Feldkirchen, DE;
Siegfried Humml, Penzberg, DE;
Klaus Schreier, Penzberg, DE;
Siemens Aktiengesellschaft, Berlin and Munich, DE;
Abstract
A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY). The respective processor (CPx) starts the read-out of the test program sections, stored in its own local memory (LMY), for localizing and identifying the error source and/or the defect causing such errors.