The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 1990
Filed:
Jun. 10, 1988
Applicant:
Inventors:
Kiyoshi Itano, Kawasaki, JP;
Kohji Shimbayashi, Kawasaki, JP;
Assignees:
Fujitsu Limited, Kawasaki, JP;
Fujitsu VLSI Limited, Kasugai, JP;
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
36518908 ; 36523008 ; 307465 ; 34082583 ;
Abstract
A programmable logic device includes an AND array; an OR array; a buffer circuit connected between the AND array and OR array; and a number of decoder arrangements operatively connected to the AND array and OR array. By constituting the buffer such that the AND array and OR array are electrically associated even in a write operation of data, namely, the buffer is brought to an enable state, a logic verify of the buffer becomes unnecessary and, accordingly, a verify/check of written data can be carried out both easily and efficiently.