Memory control subsystem

Abstract

The memory control subsystem controls and arbitrates access to a memory shared by a plurality of users. A processor with its cache and input/output devices has direct access to the memory through a direct memory access bus. The controls subsystem comprises a processor controller, a DMA controller and a memory controller. A processor request is buffered into the processor controller and is serviced immediately if the memory controller is available. A simultaneous transfer between the devices and buffers in the DMA controller is possible. If the memory controller is busy, the DMA controller causes the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards. Write requests made by the processor are buffered into processor controller and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion. A read request which does not hit the cache is sent to the processor controller which causes the cache to be updated. In case of multiple processor requests contending with a long DMA transfer, the latter is sliced into several parts, each part mapping one cache line. In case of a DMA write, the cache lines which correspond to memory positions whose content is modified by the write operation are invalidated in such a way that the processor cannot read a partially written line into the cache.