The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 1990
Filed:
Oct. 11, 1988
Katsufusa Fujita, Kitakyushu, JP;
Mitsui High-Tec Inc., , US;
Abstract
A lead frame and a method of forming the same for a semiconductor device includes a pad section (20a) and a lead section (20b) which are formed separately. The former comprises a die pad (21) upon which a semiconductor element is to be mounted, and a pair of support bars (26) extending outwardly from opposite side edges thereof. The lead section (20b) includes frame members (25), outer leads (24), inner leads (22), and tie bars (23) interconnecting the outer and inner leads together in an integral manner. The outer free or distal ends of the pad section support bars (26) are provided with first male engaging enlargements (26a), while the frame members (25) of the lead section (20b) are provided with second female recesses (25a) at predetermined positions along the longitudinal extent of the frame members (25) such that when the pad section (20a) is mounted upon or within the lead section (20b) of the lead frame (20) as a result of the engagement of the first and second engagements (26a, 25a), the support bars (26) and die pad (21) will be locked and fixed with respect to any lateral movement relative to the frame members (25) along the longitudinal extent thereof whereby the pad (21), and the semiconductor element mounted thereon, will be precisely and accurately located relative to the inner leads (22) of the lead frame (20) so as to define uniform spacing between the semiconductor element terminals and the inner leads in order to efficiently facilitate the wire bonding process to be subsequently performed between the semiconductor element terminals and the inner leads (22) of the lead frame (20).
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile