Circuit for generating non-overlapping two-phase clocks

Abstract

In order to provide for clocking master/slave flip-flops in complex circuits by means of non-overlapping two-phase clocks, a clock generator for providing two clocks signals for use with two-phase flip-flops, comprises a settable latch and a gating device. The settable latch has a data input connected to a reference source, a set input connected to receive one of the two clock signals and a clock input connected to receive the other of the two clock signals. The gating device has one input connected to receive such one of the two clock signals and a second input connected to the output of the settable latch. The output of the gating device, which corresponds to the other of the two clock signals, is connected to the clock input of the settable latch, the arrangement being such that when the settable latch has been set by a transition of the one clock signal resetting of the settable latch is enabled by the other clock signal. A digital circuit, for example an integrated circuit, may have a number of latches, each comprising, for example the first stage of a master/slave flip-flop, and such a clock generator for operating them. Preferably the latches are arranged in groups, conveniently as a macro sub-block, with a clock generator for operating each group. Preferably the settable latch is similar in construction to the latches being controlled.