The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 1990

Filed:

Jan. 06, 1989
Applicant:
Inventor:

Stephen R Tomassetti, Lewisville, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 31 ; 437 34 ; 437 56 ; 437 74 ;
Abstract

Disclosed is a proces for making a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.


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Tomassetti, Stephen. (1990). Integrated bipolar-cmos circuit isolation process for providing (U.S. Patent No. 4912054). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4912054

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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