The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 1990

Filed:

Jul. 13, 1988
Applicant:
Inventors:

Yoshito Sakurai, Yokohama, JP;

Kenichi Ohtsuki, Kanagawa, JP;

Shinobu Gohara, Yokohama, JP;

Makoto Mori, Yokohama, JP;

Akira Horiki, Yokohama, JP;

Takao Kato, Yokohama, JP;

Hiroshi Kuwahara, Kodaira, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04Q / ;
U.S. Cl.
CPC ...
370 67 ; 370 581 ; 370 60 ;
Abstract

A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.


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