The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 1990
Filed:
May. 10, 1988
Steven R Coffelt, Camarillo, CA (US);
Thomas W Durston, Camarillo, CA (US);
Harris Corporation, Melbourne, FL (US);
Abstract
An integrated services digital network (ISDN) traffic generator adapter is provided for coupling an analog traffic generator which produces a plurality of commands and analog telephone signals to an ISDN switch. In particular, first circuits provide a plurality of two-way communication links between the analog traffic generator and the ISDN switch. Each of said first circuits includes elements for converting the analog telephone signals from the analog traffic generator into a plurality of ISDN signals, including B channel information and D channel information, for said ISDN switch, and elements for converting a plurality of ISDN signals from the ISDN switch, including B channel information and D channel information, into analog telephone signal for said analog traffic generator. A processor is coupled to the plurality of first circuits for selectively addressing individual ones of said plurality of first circuits. Also, a D channel monitor is coupled to the processor for monitoring D channel communication between the first circuits and the ISDN switch. The D channel monitor can selectively monitor D channel communication between the first circuits and the ISDN switch for individual two-way communication links between the analog traffic generator and the ISDN switch in accordance with the selection of one of the first circuits by the processor.