Bit-sliced digit-serial multiplier

Abstract

A digital multiplier for multiplying together W-bit digit-serial multiplier and multiplicand signals includes a combinational array of multiplier cells arranged in N rows and W columns. A digit-serial-in/parallel-out register supplies respective bits of each successive multiplicand signal to the W columns of the array, the N rows of which receive respective bits of each successive digit of the multiplier signal. After each earlier digit of the multiplier is processed, the carry and sum bits are forwarded without column shift and with one column shift, respectively, from the final row to the first row of multiplier cells. This scrolls the operation of the W-column-by-N-row multiplier cell array, allowing it to be used M times for each word of the multiplier signal, one for each of the M digits in a W-bit word of the multiplier signal. The sum bits from the final column of multiplier cells provide the minor product output signal of the digital multiplier in digit-serial format, as each digit of the multiplier signal is processed. In processing the final digit of the multiplier, the carry and sum bits are shifted differentially by one bit place and are conveyed by shift registers to a digit-serial final adder, the full sum output of which supplies the major product output signal of the digital multiplier in digit-serial form. Supplying the minor and major product output signals in parallel permits pipelined operation of the apparatus.