The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 1990
Filed:
Dec. 16, 1985
Applicant:
Inventor:
Isamu Yamazaki, Kawasaki, JP;
Assignee:
Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki, JP;
Primary Examiner:
Int. Cl.
CPC ...
H04Q / ; H04Q / ;
U.S. Cl.
CPC ...
3408259 ; 307465 ; 307468 ; 34082591 ;
Abstract
A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.