The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 1990
Filed:
Dec. 14, 1987
Clarence A Lund, Phoenix, AZ (US);
Richard R Hamzik, Changler, AZ (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A 'false' gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers. A more compact structure is obtained.