The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 1990

Filed:

May. 16, 1986
Applicant:
Inventors:

Hiroaki Terada, Osaka, JP;

Katsuhiko Asada, Hyogo, JP;

Niroaki Nishikawa, Osaka, JP;

Souichi Miyata, Nara, JP;

Satoshi Matsumoto, Nara, JP;

Hajime Asano, Osaka, JP;

Masahisa Shimizu, Osaka, JP;

Hiroki Miura, Osaka, JP;

Kenji Shima, Hyogo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F / ; G06F / ; G11C / ;
U.S. Cl.
CPC ...
364900 ; 36492371 ; 3649265 ; 36493101 ; 36493111 ; 3649314 ; 3649397 ; 36494834 ; 364951 ; 3649501 ; 377 81 ;
Abstract

A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.


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