Semiconductor memory device

Abstract

For improvement of signal-to-noise ratio and elimination of soft errors, there is disclosed a semiconductor memory device including a plurality of memory cells, each memory cell comprising a storage capacitor having a first electrode formed in side and bottom wall portions defining a primary cavity opened at a major surface of a semiconductor substrate, a thin dielectric film covering the side and bottom wall portions and substantially dictated by the configuration of the side and bottom wall portions to define a secondary cavity, and a second electrode filling the secondary cavity and projecting from the major surface of the semiconductor substrate, a thick insulating layer covering the major surface of the semiconductor substrate and formed therein an opening substantially aligned with the secondary cavity to allow the second electrode to extend over the surface of the thick insulating layer, and a switching transistor provided on the thick insulating layer and having source/ drain regions separated from each other by a channel region, one of the source/ drain regions being connected to the second electrode, a thin dielectric film formed on the channel region, and a gate electrode formed on the thin dielectric film.