The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 1990
Filed:
Oct. 31, 1988
Geoffrey S Gongwer, San Jose, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
A logic array device having an input switch detector circuit for each input signal line leading into an array of logic gates and means for enabling the array whenever and only when a change in logic level of at least one input signal is detected. An AND array has a pull-up element connected to the device's power supply, which element is turned on by an AND array enable signal generated by a circuit responsive to switch detection. Likewise, OR gates or NOR gate/invertor combinations have a pull-down or pull-up element which is turned on by an OR array enable signal. The AND array is enabled first, followed by the OR gate or gates. The OR gate or gates is disabled first before the AND gate is disabled. Disablement of the gates when no input level switch is occurring reduces power consumption without affecting device speed, while the order of enablement and disablement prevents glitches or loss of the output signal level during enablement and disablement.