The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 06, 1990
Filed:
Nov. 10, 1988
Yasuhiko Maki, Kanagawa, JP;
Osamu Nomura, Kasugai, JP;
Fujitsu Limited, Kawasaki, JP;
Fujitsu VLSI Limited, Kasugai, JP;
Abstract
A logic circuit improves a marginal voltage of a p-channel metal oxide semiconductor (MOS) transistor which is driven through a bipolar complementary metal oxide semiconductor (CMOS) gate. The logic circuit has a bipolar CMOS gate having a CMOS gate and output stage bipolar transistors for receiving an input signal through the CMOS gate, where the CMOS gate and the output stage bipolar transistors are driven by first and second power source voltages. The first power source voltage is higher than the second power source voltage and the output stage bipolar transistors output a signal as an output signal of the bipolar CMOS gate. A p-channel MOS transistor has a gate supplied with the output signal of the bipolar CMOS gate, a source supplied with a third power source voltage, and a drain from which an output signal of the logic circuit is outputted. The third power source voltage is a predetermined value lower than the first power source voltage and higher than the second power source voltage. As a result, the turning OFF of the p-channel MOS transistor is guaranteed due to the improved marginal voltage.