The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 27, 1990

Filed:

Oct. 05, 1987
Applicant:
Inventor:

Hubert Kirrmann, Dattwil-Baden, CH;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C / ;
U.S. Cl.
CPC ...
365200 ; 365 75 ;
Abstract

In order to reduce the down time of a computer (1, 4-8) caused by a fault or interrupt in the program run, program recovery points are provided which are time-dependent or can be preset in the main program of a useful program, and when these recovery points are reached, the computer status is stored in at least one fault-tolerant archival memory (5, 6). The computer status includes the status of the variables of a useful program being executed, the register status of the processor (1) and the register status of the input/output devices of the computer. During execution of the useful program, at least a part of the current computer status is stored in a main memory (4) and copied into an archival memory (6) when a program recovery point is reached. By using a small, fast cache memory (7) between the processor (1) and the main memory (4), the write cycles in the archival memories (5, 6) may be reduced since a variable is replaced in the main memory (4) only when it is displaced from the cache memory by a variable which may have been updated several times. A further improvement is achieved by using an associative stack (8) on the bus (2, 3) as the main (4) and the two archival memories (5, 6). All modifications in the main memory (4) are simultaneously entered into the stack (8) and into an archival memory (5) without involving the processor (1). In the stack (8), address data pairs are entered in the order of occurrence, a character recording the respective state of the stack and allocating locations to new address/data pairs. At the recovery point, only updated data need to be transferred into the archival memory. The main memory (4) can be integrated into an archival memory having a read/write memory area and a fault-tolerant tributary memory area. A cascaded memory or a virtual memory of the computer can also be used for saving the computer status.


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