Fast shifter method and structure

Abstract

Normalization and scaling operations are performed by the use of the fast shifter of a micrprocessor operating in response to the system clock, rather than in response to microinstructions. By local control of the fast shifter, multiple shift steps essential to normalization and scaling operations are performed at a much faster rate than possible in the prior art wherein each bit shift must be controlled by a single microinstruction, and without the heavy cost in integrated circuit chip area that a barrel shifter requires. When a scaling or normalization operation is to be performed, the system clock is gated to the fast shifter, thus allowing the shift operation to take place in response to the gated clock. Simultaneously, when the shifting operation is taking place, a WAIT signal is provided, telling the microprocessor to postpone action on the next microinstruction until the shifter operation has been completed. The fast shifter is capable of performing either single or double bit shifts to either the right or left, as desired. The fast shifter is also use to implement the parametric shift instructions in the microprocessor instruction set, providing a similar performance enhancement to these operations.