Semiconductor memory device having stacked-capacitor type memory cells

Abstract

A semiconductor memory device including a plurality of stacked-capacitor type memory cells, each having a capacitor storing data and a transfer-gate transistor transferring data to the capacitor. The transistor includes a gate connected to a word line and formed by an insulating layer, and source and drain regions. Each of the memory cells has a first insulating layer covering the gate of the transfer-gate transistor. The capacitor in each memory cell includes a second insulating layer covering another word line adjacent to the one word line and having a larger thickness perpendicular to a plane of a substrate than that of the first insulating layer covering the gate, a second conductive layer which is in contact with one of the source and drain regions of the transistor, extends over the gate through the first insulating layer and covers the second insulating layer, a third insulating layer formed on the second conductive layer, and a third conductive layer extending over the third insulating layer. The semiconductor memory device also includes an additional conductive layer directly connected to the other of the source and drain regions of the transistor in the memory cell and extending over the gate of the adjoining transistors through said first insulating layer convering thereon. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. The semiconductor memory device further includes a peripheral circuit including transistors, each having source and drain regions and a gate electrode which is entirely covered by the second insulating layer. The source and drain regions are directly connected to wiring lines. Also disclosed is a method for manufacturing a semiconductor memory device having the above construction.