Efficiency shift register

Abstract

An improved shift register uses fewer than 2*N latches, where N is the capacity in bits of the shift register and also the propagation delay from the input to the output of the shift register in terms of the system clock. An m-phase set of clocks are used, where m is an even number larger than two and and the duration of each clock phase is one half of the period of the system clock. The latches are arranged in m/2 strings of length 2N/(m-1), instead of one long string. The strings of latches are offset with respect to each other by two phases in terms of their connection to the multiphase clock, with each successive latch in each string being enabled by the clock signal whose phase immediatedly precedes the phase of the clock signal used to enable the preceding latch in that string. A multiplexer at the output puts the data from the multiple strings of latches back into one serial output stream. The total number of latches required is N*m/(m-1), conserving a considerable number of latches for large values of N. An alternative version uses m strings of length N/(m-1) clocked by m-phase clock pulses having a duration that is a full period of the system clock. In this version, the strings of latches are offset with respect to each other by a single phase in terms of their connection to the set of multiphase clocks.