The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 1990

Filed:

Apr. 27, 1989
Applicant:
Inventors:

John C Cassani, Lexington, KY (US);

Mark K DeMoor, Lexington, KY (US);

Paul W Graf, Lexington, KY (US);

Jonathan J Hurd, Lexington, KY (US);

Christopher D Jones, Georgetown, KY (US);

Stephen F Newton, Winchester, KY (US);

David R Thomas, Cynthiana, KY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F / ; H02M / ;
U.S. Cl.
CPC ...
323222 ; 323285 ;
Abstract

A latch (29) is set by a clock (33) to turn on power switch (FET 5). The latch (29) is reset by high voltage comparator (21), by a 50 percent clock delay (35) and by a low-voltage-to-charging-current comparator (19). The voltage at turn-on is compared with a up-ramping reference (15) until it equals an operating reference (17). A temporary delay (pulse circuit 39 and gate 37) is provided before the low voltage comparison can be effective. The delay prevents response to parasitic effects across the power switch (5). Excess drive is prevented resulting from low output currents and malfunctions, and at turn-on.


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