The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 1990
Filed:
Nov. 18, 1988
Rihei Hiramatsu, Tokyo, JP;
Shigeo Watanabe, Inagi, JP;
Yasuyuki Okumura, Inagi, JP;
Jun Maruyama, Inagi, JP;
Abstract
A self-excited inverter circuit primarily includes a main transformer two switching elements e.g. the first and second (FET) switching elements, wherein capacitors at both ends of said first FET are charged during a time T.sub.1 -T.sub.2 when said first FET is turned off, and the voltage V.sub.g1 across said first FET is clamped by a charge voltage V.sub.c1 and then, a voltage V.sub.gs is applied across the gate and the source of said second FET for electrical continuity to cause the voltage to be clamped. The clamped state is maintained from T.sub.1 to T.sub.2, the saturation reactor is saturated at time T.sub.3, and V.sub.gs, which has been negative, starts to change toward O, thereby causing the first FET to change to ON; V.sub.q falls towards VPi at TP3 and further towards zero point. Thus, the voltage V.sub.q2 changes to zero to cause V.sub.gs of the second FET to become zero and the second FET to be shut off. When said voltage V.sub.q2 is clamped to a fixed value, a high -V.sub.sc (L) can be obtained in the case of Vi(L), whereas a low -V.sub.sc can be obtained in the case of Vi(H); and the continuity angle, or duty cycle, (T.sub.1 -T.sub.2)/(T.sub.1 -T.sub.3) of the first FET is naturally controlled to be kept in a desirable direction.