The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 13, 1990
Filed:
Dec. 17, 1987
Takahiko Takahashi, Tokyo, JP;
Funikazu Itoh, Fujisawa, JP;
Akira Shimase, Yokohama, JP;
HIroshi Yamaguchi, Fujisawa, JP;
Mikio Hongo, Yokohama, JP;
Satoshi Haraichi, Yokohama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
The present invention relates to a semiconductor integrated circuit device and a process for producing the same. A hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD. To electrically connect upper- and lower-level wirings in a multilayer wiring structure by a connecting wiring, the connecting wiring is electrically isolated from an intermediate-level wiring through which it extends. The above-described arrangement enables provision of a hole with a focused ion beam and formation of a metal wiring on a selective region by means, for example, optically pumped CVD. Accordingly, it is possible to effect fine machining and electrically connect together wirings inside an LSI after the completion thereof. It is therefore possible to carry out debugging, repair and a defect analysis of the LSI.