The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 06, 1990
Filed:
Feb. 01, 1988
David Potter, Acton, MA (US);
Laurence N Provost, Arlington, MA (US);
John M Baron, Grafton, MA (US);
David Stefanovic, Allston, MA (US);
Eric D Sharakan, Brighton, MA (US);
David A Sheppard, Cambridge, MA (US);
Marshall A Isman, Newton, MA (US);
Thinking Machines Corporation, Cambridge, MA (US);
Abstract
A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.