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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 4899313 B1

PDFFull Text
Date of Patent:
Feb. 06, 1990

Filed:

Apr. 06, 1988

Semiconductor memory device with an improved multi-bit test mode

Applicant:
Inventors:

Masaki Kumanoya, Hyogo, JP;

Hideshi Miyatake, Hyogo, JP;

Katsumi Dosaka, Hyogo, JP;

Yasuhiro Konishi, Hyogo, JP;

Assignee:

Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;

Attorney:

Lowe, Price, LeBlanc, Becker & Shur

Primary Examiner:

A J Heinz

Assistant Examiner:

Melissa J Koval

Int. Cl.
CPC ...
G11C / ; G11C / ;
U.S. Cl.
CPC ...
365201 ; 36518908 ; 36518904 ; 36523003 ; 371 212 ;
Abstract

A memory device provides a test mode which simultaneously carries out the function test of plural bit memory cells. In this memory device, trilevel decision is carried out based on the AND operation on the memory cell information of the selected plural bits in the single device level while bilevel decision is carried out in the board level on the basis of the OR operation on the AND result of the information of the selected plural bit memory cells and the AND result of the inverted information of the same.

Find Patent Forward Citations

Kumanoya, Masaki. (1990). Semiconductor memory device with an improved multi-bit test mode (U.S. Patent No. 4899313). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4899313

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