Novel high-speed integrated heterostructure transistors, photodetectors,

Abstract

A high-speed heterostructure planar integrated circuit includes a planar photodetector together with a transistor (either a Modulation-Doped Field Effect Transistor or a lateral p-n-p bipolar transistor). The planar photodetector includes a bottom confinement layer of a wide bandgap material, a heavily doped first conductivity-type buried layer over the bottom confinement layer, a relatively undoped higher index of refraction layer overlying the buried layer, a top confinement layer of wider bandgap material which has a lower index of refraction, a first vertical contact region of first conductivity type which extends downward to make electrical contact with the buried layer, and a second contact region of second conductivity type spaced laterally from the first contact region and extending through the top confinement layer and a portion of the undoped layer. As a result of the difference in refractive indices of undoped versus doped regions and in wide gap versus narrow gap material, light directed into one end of the photodetector is confined both laterally and vertically to the undoped layer where it is absorbed. Charge separation occurs with first conductivity carries being collected at the first contact region and the buried layer, and second conductivity carriers being collected at the second contact region.