Circuitry for and method of generating vertical drive pulse in video

Abstract

The vertical drive pulse generator comprises a gate (59) passing a vertical synchronizing signal included in received video signals in response to a control signal, a counter (60; 360) counting a clock signal (CL) of 2f.sub.H (f.sub.H : a frequency of a horizontal synchronizing signal) to generate a plurality of timing signals, a 50/60 decider (65; 365) deciding whether the vertical synchronizing signal from the gate is of the NTSC or the system and a synchronization decoder (66; 366) detecting whether the counter is reset in response to the vertical synchronizing signal passed through the gate or by a timing signal outputted by itself. One of the timing signals from the counter is selected in response to the outputs of the 50/60 decider (365; 65) and the synchronization detector (66; 366) and applied to the gate, thereby to make the gate pass a signal only when the control signal is received. When the 50/60 decider indicates that the arriving vertical synchronizing signal is of the NTSC system, the gate circuit (67; 367) opens during a period of 224 H to 296 H (H: a horizontal scanning period), while detecting the system to open the gate during a period of 268 H to 356 H. when a step-out detection circuit (66; 366) detects a step-out state, the gate opens during 224 H to 356 H. The vertical drive pulse generator further comprises a phase comparator (422) which selects and generates a signal for defining a gate period of either 260.5 H to 264 H for NTSC system or 310.5 H to 314 H for system.