The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 30, 1990
Filed:
Sep. 27, 1988
Shoichi Shimizu, Fujisawa, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
Disclosed is a logic circuit using Schottky barrier FETs comprising a plurality of circuits connected in series between first and second power supply terminals, the plurality of circuits being DCFL and/or SCFL circuits, the DCFL circuit containing a switching element and a load element, the elements being connected in a direct fashion, and consisting of Schottky barrier FETs, the SCFL circuit being a logic unit containing Schottky barrier FETs connected in a differential fashion, and a potential stabilizing means for stabilizing a potential at the junction point between the adjacent circuits, by supplementally feeding the differential current between the current consumed by the adjacent circuits.