The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 1990

Filed:

Dec. 27, 1988
Applicant:
Inventor:

Chih-Liang Chen, Briarcliff Manor, NY (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307446 ; 307570 ; 307475 ; 307542 ; 307544 ;
Abstract

BICMOS driver circuit for high density CMOS logic circuits. The BICMOS logic circuit generates a voltage swing comparable to the CMOS logic circuit voltage swing with improved delay and noise immunity characteristics. A pair of complementary bipolar transistors are connected to a CMOS logic network. The transistors have serially connected collectors forming an output node and emitters connected to opposite terminals of a bipolar voltage source. Two FET transistors are connected between the base of each bipolar transistor and a CMOS operating voltage source. The CMOS logic network will switch one or the other bipolar transistor on while the other bipolar transistor is held off by its connected FET transistor.


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