The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 1990
Filed:
May. 12, 1988
Makoto Hanawa, Kokubunji, JP;
Takuichiro Nakazawa, Kodaira, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
A content-addressable memory which has a storage bit cell (121, 122), signal supplying circuits (380, 390, 400) and comparison circuits (125, 126, 127, 128). The storage bit cell (121, 122) holds a first data (D) and a second data (D) of opposite phases. The signal supplying circuits (380, 390, 400) supply a first signal (a1) and a second signal (a1), respectively, to a first data line (180) and a second data line (190) of the storage bit cell (121, 122) in response to an input signal (A1) and a control signal (510). The first and second signals (a1, a1) are in opposite phases. The comparison circuits (125, 126, 127, 128) detect the relation between the first (D) stored in the storage bit cell (121, 122) and the first signal (a1) on the first data line (180) supplied from the signal supplying circuits (380, 390, 400) and the relation between the second data (D) stored in the storage bit cell (121, 122) and the second signal (a1) on the second data line (190) supplied from the signal supplying circuits (380, 390, 400). Wherein as part of the signal supplying circuit (380, 390, 400) circuit (400) dissolves the opposite phase relation between the first signal (a1) on the first data line (180) and the second signal (a1) on the second data line (190) in response to a control signal (510) and the input signal (A1). However, this circuit (400) does not dissolve the opposite phase relation when the input signal (A1) is '1' level and the control signal (510) is '1' level.