Thin film transistor array incorporating a shorted circuit bypass

Abstract

A thin film transistor array includes a gate bus and a source bus intersecting with each other at right angles, a thin film transistor pair disposed adjacent to the intersecting point and electrically connected to the two buses. If a short circuit is detected between the two buses, the gate bus or the source bus is severed into a separate portions to eliminate the short circuit. A bypass bus is provided to electrically connect the electrically good severed portions and to the end terminal. Such a bypass bus avoids the need for additional power supply terminals to the opposite ends of the severed bus and facilitates driving the thin film transistor by supplying the power at only one end thereof.