The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 16, 1990
Filed:
Nov. 25, 1988
Jyh-Ping Hwang, Schenectady, NY (US);
Miran Milkovic, Scotia, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A pipelined analog-to-digital converter architecture comprises three pipeline stages wherein the first stage includes a low-resolution flash A/D subconverter (10), two sample-and-hold amplifiers (12 and 14), two D/A converters (16 and 18), and two unity-gain buffers (20 and 22). Parallel-autozero analog processing is accomplished by alternately passing the analog signal through one or the other of two parallel processing channels. The sampled analog signal is delivered to the flash A/D subconverter and the D/A converters simultaneously. The residue from the D/A converters is delivered to the second stage, passing through a flash A/D subconverter (24), an additional D/A converter (26), and alternately through two comparators (28 and 30) each having a gain of eight. The second stage produces and delivers its residual voltage to the final pipeline stage comprising a flash A/D subconverter (32). The unity-gain buffers require a minimal gain-bandwidth product for a given sampling rate and allow the architecture to operate at high speed, while the first stage D/A converters provide good accuracy.