The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 1990

Filed:

Oct. 11, 1988
Applicant:
Inventor:

Keith H Gudger, Sunnyvale, CA (US);

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307465 ; 307468 ;
Abstract

A programmable logic device having an AND array receiving inputs and having programmable product term lines output to an OR array, and an output macrocell associated with each of a plurality of input/output pins. Each macrocell has a plurality of sum term lines from the OR array which may selectively be combined or left distinct, and a plurality of flip-flop registers receiving input from the combined or distinct sum lines. Each flip-flop has product term programmable clock, reset and preset lines and a dedicated feedback line into the AND array. A selection circuit is provided for selecting combinatorial output from one or more sum term lines or registered output from one of the flip-flop registers. A product term programmable output enable selects either the output or disables the output buffer so that a pin may receive input signals fed through a dedicated line into the AND array.


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