The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 16, 1990

Filed:

Oct. 11, 1988
Applicant:
Inventors:

Cecil Conkle, Palo Alto, CA (US);

Masahiko Shoji, Tokyo, JP;

Noriaki Takagi, Tokyo, JP;

Assignees:

NEC Electronics Inc., Mountain View, CA (US);

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
3072963 ; 307465 ; 307469 ; 307473 ; 364716 ; 36518907 ;
Abstract

The present invention incorporates a control mechanism in an input buffer for a gate array so that the input buffer may be directly enabled or disabled by a control signal. Hence, no power will be wasted by the unnecessary operation of gates internal to the input buffer or subsequent stages. The method of control is to couple a common control signal to one input port of each of a plurality of two-input AND gates and couple an incoming data signal to the other input port of each of the two-input AND gates. The AND gates function as input buffers and the outputs of the AND gates are applied to the subsequent stage (e.g., a gate array). Thus, a LOW control signal disables the AND gate input buffers and subsequent stages coupled to the outputs of the AND gates, regardless of whether the incoming data signals are of a HIGH or LOW state.


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