Semiconductor memory device including precharge/equalization circuitry

Abstract

The semiconductor memory has a memory array comprising word lines, complementary data lines orthogonal to the word lines, and static memory cells disposed at intersections of the word lines and between a complementary pair of data lines in a grid-like memory matrix arrangement of rows and columns. There is also included a plurality of precharge circuits for selectively setting one of two adjacent complementary data line pairs to a first voltage and the other one of the two complementary data line pairs to a second voltage, different than the first voltage, and further including equalization circuitry, thereby establishing a short-circuit between the complementary data lines of each pair of complementary data lines.