The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 1990

Filed:

Sep. 02, 1988
Applicant:
Inventors:

Minoru Yamada, Iruma, JP;

Akira Masaki, Musashino, JP;

Kazuo Sato, Tokyo, JP;

Yutaka Harada, Tokyo, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 82 ; 357 49 ; 357 51 ; 357 55 ; 357 68 ; 357 75 ; 357 84 ; 357 88 ;
Abstract

An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.


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