The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 09, 1990

Filed:

Apr. 11, 1984
Applicant:
Inventors:

Takeshi Tokuda, Osaka, JP;

Jirou Korematsu, Itami, JP;

Osamu Tomisawa, Nishinomiya, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 71 ; 357 45 ;
Abstract

A semiconductor device is designed and layed out to have a multiple-layer wiring structure and a logic gate cell structure. The multiple-layer wiring structure is constituted by wiring layers each being a vertical wiring layer for producing vertical wirings or a horizontal wiring layer for producing horizontal wirings, and either of the vertical or horizontal wiring layer is provided in plurality. One of the layers of the plurality of wiring layers is that for producing wirings which constitute input terminals of logic gates, and another layer of the plurality of wiring layers is that for producing wirings which constitute output terminals of logic gates. Wiring is carried out along each wiring grid which is provided for each of the plurality of wiring layers so that lines of different grids are alternately arranged.


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