The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 1990
Filed:
Feb. 16, 1988
Applicant:
Inventor:
Kiichiro Tamaru, Tokyo, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307480 ; 307451 ; 307511 ; 307234 ; 3072721 ;
Abstract
The logic circuit is disclosed. Even if the system is stopped while an output latch circuit is in the latching state, when an input latch circuit is latching an input signal, the logic gate remains in the precharge mode, whereas the precharge signal as generated by a precharge signal generator circuit is in the 'H' level, i.e. a precharge level. Therefore, the logic output from the logic gate is never erased. Within a period that the input and output latch circuits are both in the latching state, the system can be stopped without erasing the logic output.